The present invention relates to tri-state condition circuits and, more particularly, to a tri-state condition circuit for power-up conditions.
Televisions and other electronic devices have various complex electronic circuits that may be analog, digital, or a combination of analog and digital. Because of their complexity, good design characteristics or criteria dictate that the fewer the components the better. As well, some of these electronic circuits require different state conditions during various stages of operation. In a power-up condition, for example, it may be desirous to provide a signal to a common circuit that is not to be provided after steady state is reached, and/or vice versa.
One type of device that provides different state conditions, and thus different output results, is known as a tri-state buffer. A tri-state buffer is operable in three states, and has an input, an output, and an enable port. The enable port provides control of the tri-state buffer. When the enable is in a first state, the tri-state buffer is in a high impedance mode meaning that it will look like an open circuit. When the enable is in a second state, data or a signal on the input is allowed to pass to the output, regardless of the type of data or signal. Control of the tri-state buffer however, is typically accomplished by a high (logic xe2x80x9c1xe2x80x9d) or low (logic xe2x80x9c0xe2x80x9d) signal that is supplied by a micro controller. The enable is not controlled by a variable control circuit.
It is desirous to provide a tri-state condition circuit that is more flexible than prior art tri-state buffers. It is further desirous to provide a tri-state condition circuit that provides a tri-state conditions under power-up.
The present invention involves apparatus comprising a buffer circuit and a control circuit that generates a control signal for controlling the mode of operation of the buffer circuit. The buffer circuit has a first mode of operation during which an output signal produced by the buffer circuit exhibits one of first and second logic states in response to respective logic states of an input signal, and having a second mode of operation during which the output signal exhibits a third logic state independent of the logic states of the input signal. The control circuit generates a control signal that causes the buffer circuit to selectively operate in one of the first and second modes of operation. The control circuit generates the control signal only directly in response to operating power being applied to the control circuit. The control circuit generates the control signal for causing the buffer circuit to operate in the second mode of operation only for a predetermined interval subsequent to operating power being applied to the control circuit. The control circuit generates the control signal for causing the buffer circuit to operate in the first mode of operation at all times other than the predetermined interval.
Another aspect of the invention involves operating circuitry coupled to receive the output signal produced by the buffer circuit and being responsive to the third logic state of the output signal of the buffer circuit for entering a normal mode of operation subsequent to the application of operating power to the operating circuitry.